[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]]
[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]
== Interrupt generation ==
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
Interrupts on the CPC The CPU maskable interrupts are created generated by the Gate Array based on settings from the CRTC. The Gate Array has an This is done by using a 6bits internal counter R52 (and monitoring the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signalHSync and VSync signals produced by the CRTC.
On all CRTCsevery falling edge of the HSync signal, R52 interrupts always start 1µs after the end of an HSYNCGate Array will increment the counter by one. But on CRTCs 3/4When the counter reaches 52, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC register 3settings (one HSync every 64us) this will produce a 300Hz interrupt rate.
R52 will return to 0 and When the CPU acknowledge the Gate Array will send an interrupt request on any of these conditions:* When (eg. it exceeds 51* By setting bit4 of is going to jump to the RMR register of interrupt vector), the Gate Array to 1* At the end will reset bit5 of the 2nd HSYNC after counter, so the start of the VSYNCnext interrupt can't occur closer than 32 HSync.
When the Gate Array sends an interrupt request:*If the interrupts were authorized at the time of the requesta VSync occurs, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared will wait for two HSync and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.:
[https://shaker* If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0.logonsystem* If the counter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0.eu/ACCC1.8-EN.pdf Source]
Note: On Amstrad PlusThis 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt management system service routine is seriously beefed up. See the [[ASIC]] wiki pageeventually executed.
<br>So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register.
== CSYNC signal ==The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines…
The HSYNC and VSYNC signals are received from Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[CRTCASIC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the displaywiki page.
When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black=== Timings ===[https://www. If the HSYNC is set to 14 characters then black will be output for 14µsgrimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
If a graphics mode change is pending, The INT signal (active low) produced by the HSYNC pulse width needs to be at least 2µs for Gate Array to change , is a short pulse of 1.4us and starts right after the falling edge of the HSync signal (produced by the graphics modeCRTC).
C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs === DI in peace ===[https://acpc.me/ACME/FANZINES Source: Amslive No4 (signal is cut short if HSYNC width is greater than 6Madram).]
For example, if CRTC R2=46, and CRTC HSYNC width The GA maintains its int request until it is 14 chars then C-HSYNC starts at 48 and lasts only until 51 includedaccepted. On Gate Array, even if RST #38 occurs not after the duration of the CRTC VSYNC is reduced to 2 µsecondsEI, but after the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to instruction following the monitor. While on ASIC/Pre-ASIC, EI (the CRTC VSYNC must be active as long as the C-VSYNC signal is sent Z80 needs time to the monitorclean up its act). The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:* H06 counts Even if the number of CRTC characters processed during an HSYNC. H06 is incremented int isn't validated by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2Z80, and changes IC (interrupt counter) continues on its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6merry way.* V26 counts But after the number of HSYNCs occuring during EI, a VSYNC. V26 is incremented by test similar to the Gate Array when one seen for the CRTC signals an end of HSYNC. VBL is performed: The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC interrupt is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processedgenerated anyway, the Gate Array stops outputting the palette colour black.but:* If CRTC VSYNC is activated again while V26 is still in progressIC < 32, then V26 IC is reset to 0 and starts counting up again unchanged (the HSYNC pulses. The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC. C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal next int will then be produced by the Gate Array is 1 when inactive and 0 when active21 to 52 lines later). On a CPC monitor, the CSYNC * Otherwise bit 5 of IC is rendered in "absolute black"set to zero. It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter. [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Source]<br>
== Controlling the Gate Array ==
== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]