Changes

* The eagle schematics indicate INT is triggered, but the PCB drawings indicate [[NMI]] is connected. * the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.* Has a write only I/O port &FBFB/&FAFB (partially decoded. where A10=0, and A2=0). A8 controls of the port address (when '1'?) is used to 'activate' the ROMDIS/signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signalcausing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.It's not clear how the entire space can be written to. * The unit has a switch for load/save, looks like A12 is driven depending on that. All the above has been derived from schematics so may be wrong. This needs testing.