Changes

The CPC6128 second page of 64KB RAM is controlled by a PAL 16L8 chip. It has the Amstrad part number 40031.

This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the (even in C3 mode). The [[Gate Array]] can only access the unmapped Base 64k page of RAM.

== PAL I/O port = Page order ===

Note that no settings RAM expansions are stored in the Gate Array itself regarding the MMR registernot required to conform to any page order. But For example, the PAL and Gate Array share an I/O port address so [[Dk'tronics Silicon Disc]] is a 256k RAM expansion that it appears provides Pages 4 to 7. RAM expansions can even be at an adjacent address range. For example, the [[Y-MEM]] is a 512k RAM expansion that uses the &7Exx range instead of the usual &7Fxx. Given this diversity of RAM expansions, [[SymbOS]] does the same chip right thing by testing each 64k page individually to detect the programmeravailable RAM. <br>

For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PALThe CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does.

Furthermore, if bit14=0 then CRTC will be selected tooSo external RAM expansions can differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion].

Note: <br> == PAL and Pre-ASIC == The PAL component is integrated inside the Pre-ASIC chip. But it is disabled by default on the CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does. So external RAM expansions can differ  It is possible to enable it by doing an hardware modification explained in their behaviour regarding &C3 modethat article: [[Arnold4]] <br> == PAL and ASIC == The PAL component is integrated inside the ASIC chip. But it is disabled by default on the 464 Plus and GX4000. See [https://www.cpcwiki.eu/forum/amstradnews-cpc-hardwareevents/464announcing-preasicsonic-c3gx-rama-configurationnew-andepisode-romof-7sonic-the-hedgehog-for-amstrad-gx-4000/ Discussion msg248436/#msg248436 Source] Besides, most existing RAM expansions except Gemini have a problem. [https://pulkomandy.github.io/shinra.github.io/gemini.html Source] The issue is specific to the Amstrad Plus machines which add yet another complication to the memory mapping handling on CPC machines. Basically, the forum] ASIC can be memory mapped and hide a part of the RAM. This works well for the main RAM bank, and on the CPC, it also works for the internal extra 64K of RAM, which can be mapped at the same address. If you try to map both the RAM and the ASIC there, the ASIC is mapped and the RAM is not accessible until the ASIC is moved out of the way. Unfortunately, memory expansions designed for the classic CPC does not take this into account. For some of them, because they were designed before the Amstrad Plus ASIC existed, and for some, the designers didn't think of it or decided it was not important. As a result, these extensions can enter in conflict with the ASIC, which will result, at best, in software crashes, and at worst, in '''damage to the hardware'''. Software that is known to hit this problem with existing memory expansions: *[https://www.cpcwikicpc-power.eucom/forumindex.php?page=detail&num=14940 CRTC3 demo]*[https:/amstrad/soundtrackerdma.cpcscene.net/doku.php?id=en:download Soundtracker DMA] <br> == Signals used for RAM management == The following signals are used for RAM management and are available on the expansion connector. === RAMDIS ===(Internal RAM Disable; Input to Internal RAM) When RAMDIS="1" the internal RAM of the CPC/CPC+/KC Compact is forced inactive.e.g. a ram-cpcexpansion device would use this signal to override the internal RAM selection with the RAM on the device. The internal RAM would be forced inactive, and the RAM on the ram-hardwareexpansion would be actived. === /dk%27tronicsRAMRD ===(RAM Read; Output from Gate-Array) When /RAMRD="0" a ramread operation is active. This signal is generated by the Gate-c3Array. This signal will be "0" when:* A15=A14="0" and bit 2 of the Gate-selectionArray rom configuration register is set to 1. (lower ROM disable)* A15=A14="1" and bit 3 of the Gate-464/ Another discussion]Array rom configuration register is set to 1. (upper ROM disable)* A15 is not equal to A14.

The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:

Original version from Porchy suffer suffers from a bad handling of the RAMDIS signal. This cause It caused screen artefact when accessing an external extension RAM like XMEMexpansion.

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category: Memory expansions]][[Category:Programming]] [[Category:Datasheet]]