== Interrupt generation ==
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
Interrupts on the CPC The CPU maskable interrupts are created generated by the Gate Array based on settings from the CRTC. The Gate Array has an This is done by using a 6bits internal counter R52 (and monitoring the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signalHSync and VSync signals produced by the CRTC.
On all CRTCsevery falling edge of the HSync signal, R52 interrupts always start 1µs after the end of an HSYNCGate Array will increment the counter by one. But on CRTCs 3/4When the counter reaches 52, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC register 3settings (one HSync every 64us) this will produce a 300Hz interrupt rate.
R52 will return to 0 and When the CPU acknowledge the Gate Array will send an interrupt request on any of these conditions:* When (eg. it exceeds 51* By setting bit4 of is going to jump to the RMR register of interrupt vector), the Gate Array to 1* At the end will reset bit5 of the 2nd HSYNC after counter, so the start of the VSYNCnext interrupt can't occur closer than 32 HSync.
When the Gate Array sends an interrupt request:*If the interrupts were authorized at the time of the requesta VSync occurs, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared will wait for two HSync and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.:
[https://shaker* If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0.logonsystem* If the counter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0.eu/ACCC1.8-EN.pdf Source]
Note: On Amstrad PlusThis 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt management system service routine is seriously beefed up. See the [[ASIC]] wiki pageeventually executed.
<br>So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register.
== CSYNC signal ==The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines…
The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display. When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs. If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode. C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6). For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included. Note: On Gate ArrayAmstrad Plus, even if the duration of the CRTC VSYNC interrupt management system is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitorseriously beefed up. While on ASIC/Pre-ASIC, See the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor. The Gate Array (and [[ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black. If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses]] wiki page.
The HSYNC signal from the CRTC is 0 when inactive and 1 when active=== Timings ===[https://www. Same for VSYNCgrimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC INT signal (active low) produced by the Gate Array , is a short pulse of 1 when inactive .4us and 0 when activestarts right after the falling edge of the HSync signal (produced by the CRTC).
On a CPC monitor, the CSYNC is rendered === DI in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighterpeace ===[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]
[https://shakerThe GA maintains its int request until it is accepted.logonsystemRST #38 occurs not after the EI, but after the instruction following the EI (the Z80 needs time to clean up its act).eu/ACCC1Even if the int isn't validated by the Z80, IC (interrupt counter) continues on its merry way.8-EN.pdf Source]But after the EI, a test similar to the one seen for the VBL is performed: The interrupt is generated anyway, but:* If IC <br>32, IC is unchanged (the next int will then be produced 21 to 52 lines later).* Otherwise bit 5 of IC is set to zero.
== Controlling the Gate Array ==