Changes

The SP0256 can address 60Kbytes (480Kbits) of internal or external ROM, however, usally the ROMs are only 2Kbytes (16Kbit). The ROM contains plain program code, without any kind of data arrays.

The upper 4bit of the program counter cannot be zero, so the memory starts at byte-address 1000h, and ends at FFFFh. The first 512 bytes are entrypoints, usually containing JUMP opcodes for up to 256 allophones or words.

The opcodes and their parameters are transferred serially, LSB first (except, for some reason, the JUMP/CALL/SETPAGE "Target" values are MSB first).

The JUMP/CALL/RET opcodes can address only byte-aligned addresses, however, opcodes aren't always multiples of 8bits in size, so following opcodes may begin on any bit boundary.

0000b SETPAGE/RET Set Page for JUMP/CALL, or Return from CALL

0110b SETMSB_23 Load Amplitude, MSBs of 2 or 3 Coeffcients

0111b LOAD_PA Load Pitch, Amplitude

1000b LOAD_ALL Load All Parameters (at full 8bit precision)

1001b DELTA_56 Add Delta to Amplitude, Pitch, 5 or 6 Coefficients

1101b CALL Jump to Subroutine (12-bit PAGE-Relative Address)

1110b JUMP Jump to 12-bit PAGE-Relative Address

1111b PAUSE Silent Pause

4 Target bit8-11 (in reversed bit-order!)

CALL pushes the 16bit byte-aligned return address onto stack, and marks the stack as not empty. The previous contents of the stack are lost (the stack is only one entry deep).

4 Zero for RET (00h=Return)

Note: HALT state stops program execution, but does not stop the sound generator - to obtain silence, issue a short PAUSE (or another opcode that sets amplitude=0).

4 Target bit12-15 (in reversed bit-order!) (01h..0Fh=Page)

(Note that address loads via ALD appear to ignore PAGE, and set the four MSBs to $1000. They do not modify the PAGE register, so subsequent JUMP/CALL instructions will jump relative to the current value in PAGE.)

2 Repeat Count bit4-5 (expands the next ONE opcode that uses 4bit repeat)

Some opcodes have optional parameters (for example "(8)" means an optional 8bit parameter), which is included in the opcode only when EXTRA=1.

4 Repeat Count

Provides a silent pause of varying length. The pause behaves identially to a pitch with Amplitude=0 and Period=64. All coefficients are cleared, as well.

4 Repeat Count

8 Pitch (00h=Noise)

4 Repeat Count

8 Coeff B4 signed ;\coeff pair 4

8 Coeff F4 signed ;/

8 Coeff B5 signed ;\coeff pair 5

8 Coeff F5 signed ;/

Notes: The pitch and amplitude deltas that are available when EXTRA=1 are applied every pitch period, not just once. Wraparound may occur. If the Pitch goes to zero, the periodic excitation switches to noise.

4 Repeat Count

3/6 Coeff B2 Bit4/1..6 unsigned ;\coeff pair 2 ;

5/6 Coeff F2 Bit3/2..7 signed ;/ ;/

4/6 Coeff B3 Bit3/1..6 unsigned ;\coeff pair 3

6/7 Coeff F3 Bit2/1..7 signed ;/

Sets the unspecified coefficients to 0. The "unsigned" B0,B1,B2,B3 values are zero-expanded from N bits to (N+1) bits, and are then copied to the upper (N+1) bits of the register.

4 Repeat Count

6/7 New F3 MSBs signed ;\

6/8 New F4 MSBs signed ; Opcode SETMSB_23 only

(8) New F5 MSBs signed (when EXTRA=1 only) ;/

(0) Set F5=0 and B5=0 (when EXTRA=0 only)

All other coefficient bits are unaffected (ie. all coefficients that aren't accessed by the specific opcode, as well as LSBs of accessed coefficients).

4 Repeat Count

4/5 F3 6,7 MSBs signed ;/

4/5 B4 x,8 MSBs signed ;\ <---- DELTA_56: x=6, and DELTA_23: x=7 (?)

4/5 F4 6,8 MSBs signed ;/

(5) B5 (8) MSBs signed ;\ ;\when EXTRA=1 only

The update to the amplitude register is a normal 2s complement update to the entire register. This means that any carry/borrow from the mantissa will change the value of the exponent. The update doesn't know anything about the format of that register.

According to Joe and Frank, a repeat count of zero "causes the instruction to not execute" (and not to fetch any of its following paramters, so the opcode becomes only 8bits long; or to fetch, but not apply them?), however, they've also mentioned that "conflicting documentation suggests there's more going on".

Bit fields narrower than 8 bits are MSB justified unless specified otherwise, meaning that the least significant bits are the ones that are missing. These LSBs are filled with zeros.

When updating filter coefficients with a delta-update, the microsequencer performs plain 2s-complement arithmetic on the 8-bit value in the coefficient register file. No attention is paid to the format of the register.