* ''This is adapted from an article about the "Cathode Ray Tube Controller" by CPC scene member [[ChaRleyTroniC]]''
The '''CRTC''' (Cathode Ray Tube Controller) helps to generate the video signal of the Amstrad CPC.
|7||Vertical Sync Position||x0000000||30||When to start the VSync signal, in characters.
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|8||Interlace and Skew||CCDDxxII||0||CC: Cursor Skew (Only in CRTC0CRTCs 0, 3 and 4). DD: Display Skew (Only in CRTCs 0, 3 and 4). 00: No interlace; 01II: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode.
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|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
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|10||Cursor Start Raster||xBP00000||0||Cursor signal is not used on CPCconnected to the Gate Array but is provided to the expansion port. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
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|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
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|12||Display Start Address (High)||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC Reg. 12 (ie. bit11 of Display Start Address)
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|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"|Write Only
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|10||Cursor Start Raster||Write Only||Write Only||Read Only/Write
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|11||Cursor End Raster||Write Only||Write Only||Read Only/Write
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|12||Display Start Address (High)||Read/Write||Write Only||Read/Write
UM6845:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
UM6845R:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
MC6845:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
Pre-ASIC/ASIC:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
=== Interlace and Skew (R8) ===
UM6845:
*Bits 7..6 define the skew (delay ) of the CUDISP signal(00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 5..4 define the skew (delay ) of the DISPTMG signal(00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 3..2 are ignored.*Bits 1..0 define the interlace mode(00 = No interlace; 01 = Interlace Sync; 10 = No Interlace; 11 = Interlace Sync and Video).
UM6845R:
*Bits 7..2 are ignored.*Bits 1..0 define the interlace mode.
MC6845:
*Bits 7..2 are ignored.*Bits 1..0 define the interlace mode.
Pre-ASIC/ASIC:
*Bits 7..6 are ignoreddefine the skew (delay) of the CUDISP signal.*Bits 5..4 define the skew (delay ) of the DISPTMG signal.*Bits 3..2 are ignored.*Bits 1..0 define the interlace mode. Interlace modes:
[[File:CRTC Interlace modes.png]]
=== ASIC/Pre-ASIC and R10/R11 ===
The cursor raster registers R10/R11 act as status registers when read on Types 3 & 4. They behave as normal cursor raster registers upon write.
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