*For RAM banking settings see Register 3 of the [[Gate Array]] (Note that no settings are stored in the gate array, but the PAL and gate array share an I/O port address).
*Bit 14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0, 1, 2. It can be at 0 or 1 on CRTCs 3 and 4. For compatibility reasons, it is strongly advised to always set bit 14 to 1 to select PAL.
*[[Gate Array and ASIC Pin-Outs]]
[[Category:Datasheet]]