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CRTC

8,501 bytes removed, 29 May
The 6845 '''[[File:CRTC''' Type 0.jpg|thumb|right|CRTC Type 0 (Cathode Ray Tube ControllerHitachi) chip was created by Motorola in 1977. It works with the [[Gate Array]] to generate the video signal on the Amstrad CPC. This chip is also used in the [[BBC MicroFile:CRTC UMC Type 0.png|thumb|right|CRTC Type 0 (UMC)]], [[Sharp X1File:CRTC Type 1.png|thumb|right|CRTC Type 1]], [[MicroBeeFile:CRTC6845-Type2.jpg|thumb|right|CRTC Type 2]], [[Commodore PET]] and the CGA graphics card for [[IBM PC]].
NOTES: * This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for 6845 '''CRTC and one for Gate-Array''' (Cathode Ray Tube Controller) chip was created by Motorola in 1977. In this document It works with the term '[[Gate-Array' is used, but this also applies ]] to generate the ASIC.* Much information has been drawn from video signal on the [https://shaker.logonsystem.eu/ CRTC Compendium] documentation and condensed for clarity. For details, timing diagrams, code examples, coding tips, and more, refer to that documentationAmstrad CPC.
<br>This chip is also used in the [[BBC Micro]], [[Lynx|Camputers Lynx]], [[EG2000 Colour Genie]], [[Sharp X1]], [[MicroBee]], [[Commodore PET]] and the early graphics cards (MDA, Hercules, CGA, Plantronics Colorplus) for [[IBM PC]]. And it is found in some [https://www.msx.org/wiki/Hitachi_HD6845 MSX1 expansions], providing an 80-column text mode. It's important to note that the CRTC chip is primarily designed for character-based displays. It explains why, on the Amstrad CPC, the video memory is organized into a grid of characters rather than a purely linear bitmap. NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
== Overview ==
The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.
The CRTC is a simple chip really . It is just a bunch made up of counters and equality operators, tied by simple logic. But All the devil is in the details, and that's what we will discuss in this articlecomplexity stems from its multiple independent implementations with their subtle differences.
The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.
This table lists the known ICs used, with their part number, manufacturer and type number.
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!|''Part number!''||''Manufacturer!''||''Type number (note 3)''
|-
|HD6845S||Hitachi||0
3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.
The As far as I know, the type number system was originally used by demo programmers.
It is possible to detect the 6845 present using software methods, and this is done to:
* In most cases, the type of the detected 6845 is reported.
4. As far as I (Kevin Thacker) know, the KC compact used HD6845R only.
<br>== Timings and relating with Z80 instructions count ==
== Some informations like : how many Z80 instructions can Ifit within a scan line ? Within a screen ? Etc... See http:/O access timings == The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Arraywww. {| class="wikitable"|+! Instructions !! Duration !! Icpcwiki.eu/O CRTCs 0forum/1programming/2 !! I/O CRTCs 3/4|frame-| OUT (C),r8 || 4 µsec || '''3rd µsec''' || 4th µsec|flyback-| OUT (C),0 || 4 µsec || '''3rd µsec''' || 4th µsec|and-interrupts/msg25106/#msg25106| OUT (nTo be extracted/edited to conform to wiki good practices),A || 3 µsec || 3rd µsec || 3rd µsec|-| OUTI || 5 µsec || 5th µsec || 5th µsec|-| OUTD || 5 µsec || 5th µsec || 5th µsec|-| IN r8,(C) || 4 µsec || 4th µsec || 4th µsec|-| INI || 5 µsec || '''4th µsec''' || '''4th µsec'''|-| IND || 5 µsec || '''4th µsec''' || '''4th µsec'''|-| IN A,(n) || 3 µsec || 3rd µsec || 3rd µsec|} <br>.
==Programming==
The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.
The recommended I/O port addresses are:
{| class="wikitable"
|-
!I/O port address
!/CS (A14)
!R/W (A9)
!RS (A8)
!Function
!Read/Write
|-
|&BCxx||0||0||0||Select 6845 register||Write only
|-
|&BDxx||0||0||1||Write to selected internal 6845 register data||Write only
|-
|&BExx||(note 0||1)||0||* CRTCs 0/2: —* CRTC 1: Read Status Register* CRTCs 3/4: Read from selected internal 6845 register||Read only
|-
|&BFxx||(note 0||1)||1||Read from selected internal 6845 register||Read only
|-
|}
'''NOTES''' 1. The function of these I/O ports is dependant on the CRTC type 2. The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the CRTC is not aware of the CPU bus 's I/O direction. Therefore, if you perform executing an IN instruction to the select or write functions, it will write data to causes the CRTC from to write the current unpredictable data on provided by the high-impedance busto its registers. <br>
==Video Memory Address (VMA)Addressing==
The VMA of the [[Gate Array]] is constructed from the CRTC MA and RA signals:
=== Overscan bits ===
It's is possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.
.------- REG 12 --------. .------- REG 13 --------.{| class="wikitable" | + CRTC Display Start Address| -! colspan="8" | Register 12! colspan="8" |Register 13 |-! 15 !! 14 !! 13 !! 12 !! 11 !! 10 09 08 07 06 05 04 03 02 01 00!! 9 !! 8 .! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0|--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--. |X |X | | | | | | | | | | | | | | | colspan="2" |Unused '--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--' '--.--'--.--'---------------.-----------------' | | colspan="2" |Video Page | colspan="2" | '------> Offset for setting videoramPage Size | colspan="10" | Start Address (1024 positions) Bits 0..9 | | | '-------------------------> Video Buffer | '-------------------------------> Video Page}
.{| style="white-space: nowrap;"|-.|{| class="wikitable" style="margin-right: 32px"|-.---------------. .--.--.--------------. |! Bit 13|!! Bit 12| !! Video Page | |11|10| Video Buffer | |--|--0 |---------------| |--|--|--------------| | 0| 0| 0000 - 3FFF | -| 0| 0| 16KB 1 | |4000 --7FFF|--|---------------1 | |--0 || 8000 --BFFF|--------------| | 0| 1| 4000 - 7FFF | 1 | 0| 1C000 - FFFF| 16KB }| {|--class="wikitable"|--! Bit 11 !! Bit 10 !! Page Size|---------------| 0 |--|--0 |--------------|16KB | 1-| 0| 8000 - BFFF | | 1| 0| 16KB | |--|--1 |---------------| 0 |--|--16KB|--------------| | 1| 1| C000 - FFFF | | 1| 1| '''32KB''' |}|} <br> === Coarse hardware scrolling === The start address can be manipulated to achieve horizontal and/or vertical hardware scrolling: '*To move right: <code>start_address := start_address + 1</code>*To move left: <code>start_address := start_address -1</code>*To move down: <code>start_address := start_address + R1</code>*To move up: <code>start_address := start_address -'-R1</code> However, it is a position in word (16 bits), not in byte. So, the screen will move two bytes at a time horizontally. Also, the precision will be one CRTC character vertically. The first game that used R12/R13 for both horizontal and vertical hardware scrolling is [https://www.cpc-power.com/index.php?page=detail&num=1839 Roland on the Ropes], released in 1984. The following BASIC program demonstrates the coarse scrolling by setting the R12 and R13 registers based on keyboard input: <pre>10 ma%=020 IF INKEY(1)=0 THEN GOSUB 10030 IF INKEY(2)=0 THEN GOSUB 30040 IF INKEY(8)=0 THEN GOSUB 50050 IF INKEY(0)=0 THEN GOSUB 70060 GOTO 20100 '---------------right110 ma%=ma%+1: GOSUB 900: RETURN300 ' down310 ma%=ma%+40: GOSUB 900: RETURN500 'left510 ma%=ABS(ma%--1): GOSUB 900: RETURN700 'up710 ma%=ABS(ma%--40): GOSUB 900: RETURN900 'set R12 and R13910 l%=ma% AND 255: h%=&30 OR ((ma%\256) AND 3) :OUT &BC00,13:OUT &BD00,l%: OUT &BC00,12:OUT &BD00,h%930 RETURN</pre> Which looks like the following: [[File:CRTC-Coarse-scroll.gif]] <br> === Advanced hardware scrolling === To achieve smoother hardware scrolling, other tricks are required in complement to R12/R13. Usually, R3 is used for smooth horizontal scroll and R5 for smooth vertical scroll. A good example of smooth hardware multidirectional scrolling game on CPC is [https://www.cpc-power.com/index.php?page=detail&num=2119 Super Cauldron], released in 1993. Everything you need to know about hardware scrolling on CPC can be found [https://www.cpcwiki.eu/forum/programming/hardware-scrolling----------'21687/ there].
<br>
== Split screen (aka Rupture) ==
While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions.
 
This is useful for defining different scrolling zones in your screen frame. For example, it was used for hardware parallax scrolling in the game [https://www.cpc-power.com/index.php?page=detail&num=1307 The Living Daylights], released in 1987. [https://www.cpcwiki.eu/forum/programming/the-living-daylights-extra-colours-in-mode-1-rasters-screen-splits/ Source]
 
And this is basically the bread and butter of innumerable CPC demos.
Some rules of thumb [https://www.cpcwiki.eu/forum/programming/advice-on-split-screen-code/msg242186/ Source]:
Total height of all splits must be 39.
<br> == Screen wobbling and Fine horizontal hardware scroll == Beware, these effects rely on invalid HSYNC video signalsThe [https://www. They are badly supported on modern displayscpcwiki. When R2 increases eu/forum/programming/interrupt-positions-with-various-sized-screens/ IntPos tool] by 1, Kevin Thacker can help visualize the potential split screen is shifted to the left by 16 mode2 pixels. When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels. When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels. When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixelsareas.
The shift Note: If all you want is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used multiple graphics modes in the same frame, you don't need to get even finer horizontal control by modifying R2touch the CRTC at all. More information here: [https://www.cpc-power.com/cpcarchives/R3 on each raster lineindex.php?page=articles&num=184 Multi-Mode Graphique (FR)]
<br>
CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.
However, this signal is provided to the expansion [[Connector:Expansion port]]. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.
<br>
==== Interline border ====
On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.
 
If border skew is used, the border byte will skew and change into a full character-width border instead.
 
==== Border conflict ====
If R1=0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER.
 
If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.
To see the border bytes with your own eyes, type this BASIC line after reset:
</pre>
<br>== HSYNC and VSYNC ==
== On CPC, HSYNC ==and VSYNC from the CRTC are passed into the Gate-Array.
The When HSYNC signal from the CRTC is not directly connected to active Gate-Array outputs the displaypalette colour black. It If the HSYNC is passed set to the [[Gate Array]] 14 characters then black will be output for further modification. See its wiki page14us.
While The HSYNC is active, all modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC counters continue to increment normally and addresses continue lasts 4us when HSYNC length is greater or equal to be generated6.
On all CRTCsIf R2=46, while an and HSYNC width is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC14 then monitor hsync starts at 48 and lasts until 51.
=== Contiguous HSYNCs ===On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array.
On CRTC 0, two HSYNCs cannot be contiguousThe VSYNC is also modified before being sent to the monitor. They are always separated by at least 1 CRTC character. What It happens is that when HSC=R3 and HCC=R2, two lines* after the condition HSC=R3 takes precedence over VSYNC from the condition HCC=R2 CRTC and HSYNC stay two lines (same cut rule if VSYNC is stoppedlower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.
On CRTCs 1/2/3/4Using CRTC1, HSYNCs can be contiguousVSYNC width value 0 means a value of 16.
=== Signal delay === On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character. But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal.  So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. === Discolouration effect === On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse. So even when a fully valid C-HSYNC pulse of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors. <br> == VSYNC == The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page. While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated. On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.  On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC. === Ghost VSYNC === On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled. === Mid-VSYNC === On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2. As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. === PPI VSYNC === The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved. In the CRTC Compendium, chapter 7.3 "Fake VSYNC", [[Longshot]] has also experimented with reversing the direction of PPI port B to output a VSYNC signal from the PPI to the Gate Array. This technique is not for the faint of heart! <br> == CRTC registers 6845 Registers ==
The Internal registers of the 6845 are:
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
!Register Index!Register Name!Range!CPC Setting!Notes|-|0||Horizontal Total (-1)||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs1µs.
|-
|1||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position ||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines . (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these) ; HSync pulse width in characters.
|-
|4||Vertical Total (-1)||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|6||Vertical Displayed||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync Positionposition||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||CCDDxxIIxxxxxx00||0||CC00: Cursor Skew (Only in CRTCs 0, 3 and 4). DDNo interlace; 01: Display Skew (Only in CRTCs 0, 3 and 4). IIInterlace Sync Raster Scan Mode; 10: No Interlace ; 11: Interlace Sync and Video Raster Scan Mode.
|-
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor signal is not connected to the Gate Array but is provided to the expansion portused on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC R12 (ie. bit11 of Display Start Address)
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|15||Cursor Address (Low)||00000000||0
|-
|16||Light Pen Address (High)||xx000000||||Read Only. On CRTC1, bit6 of Status register goes to 0 when R16 is read
|-
|17||Light Pen Address (Low)||00000000||||Read Only. On CRTC1, bit6 of Status register goes to 0 when R17 is read
|-
|}
=== Register access ===registers 18-31 read as 0, on type 0 and 2.registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.
On all CRTCs, only the 5 least significant bits of the selected register number are considered to write to a register. The other bits are ignored.<br>
On CRTCs 0/1/2, only the 5 least significant bits of the selected register number are considered to read a register.=== Screen size ===
On CRTCs 0/We can calculate the screen size in words by multiplying R1 x R6 x (R9+1). And then multiplying the result by 2, registers 18-31 read as 0to have the screen size in bytes.
On With the default CRTC values, we obtain 40 x 25 x (7+1, registers 18-30 read as 0, register 31 reads as &FF) x 2 = 16000 bytes.
On CRTCs 3/4, So we can observe that only part of the 3 least significant bits 16384 bytes (=16KB) page of the selected register number are considered to read a register, according to the following table:VRAM is actually displayed on screen.
{| class="wikitable"!Nb!Register!Definition|-|0||R16||Light Pen Address (High)|-|1||R17||Light Pen Address (Low)|-|2||R10||Cursor Start Raster|-|3||R11||Cursor End Raster|-|4||R12||Display Start Address (High)|-|5||R13||Display Start Address (Low)|-|6||R14||Cursor Address (High)|-|7||R15||Cursor Address (Low)|}<br>
<br>== CRTC Differences ==
== CRTC register In this section I will attempt to identify all the differences ==between each CRTC.
The following tables list the functions that can be accessed for each type:
Type 0
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!|''b1!''||''b0!''||''Function!''||''Read/Write ''
|-
|0||0||Select internal 6845 register||Write Only
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read Only only
|-
|}
Type 1
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!|''b1!''||''b0!''||''Function!''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read Only only
|}
Type 2
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!|''b1!''||''b0!''||''Function!''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read Only only
|-
|}
Type 3 and 4
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!|''b1!''||''b0!''||''Function!''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read Only only
|-
|}
It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type:
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!|rowspan=2|''Register Index!''||rowspan=2|''Register Name!''||colspan=34|''Type''
|-
!|0!||1 & ||2!||3 & ||4
|-
|0||Horizontal Total (-1)||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|2||Horizontal Sync Position||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|3||Horizontal and Vertical Sync Widths||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|4||Vertical Total (-1)||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|5||Vertical Total Adjust||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|6||Vertical Displayed||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|7||Vertical Sync Positionposition||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|8||Interlace and Skew||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|10||Cursor Start Raster||Write Only||Write Only||Read/WriteOnly||(note 2)||(note 3)
|-
|11||Cursor End Raster||Write Only||Write Only||Read/WriteOnly||(note 2)||(note 3)
|-
|12||Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write(note 2)||(note 3)
|-
|14||Cursor Address (High)||colspan=3 style="text-align: center;"Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|15||Cursor Address (Low)||colspan=3 style="text-align: center;"Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|16||Light Pen Address (High)||colspan=3 style="text-align: center;"Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|17||Light Pen Address (Low)||colspan=3 style="text-align: center;"Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|}
'''Notes'''
* 1. On CRTCs type 0/and 1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.
* CRTC types 3 and 4 are identical in every way, except 2. See the document "Extra CPC Plus Hardware Information" for the unlocking mechanism, split screen, hardware soft scroll and 8-bit printer port functionalities specific to the ASICmore details.
* See 3. CRTC type 4 is the document "Extra CPC Plus Hardware Information" for more detailssame as CRTC type 3. The registers also repeat as they do on the type 3.
<br> === R10/R11 on ASIC/Pre-ASIC === The cursor raster registers R10/R11 act as status registers when read on CRTCs 3/4. They behave as normal cursor raster registers upon write. {| class="wikitable"! R10 - Bit number! Bit value! Event|-|0|1|C0=R0|-|1|0|C0=R0/2|-|2|0|C0=R1-1 Horizontal and Vertical Sync (if R0>=R1)|-|3|0|C0=R2|-|4|0|C0=R2+R3|-|5|01|R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7)R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)|-|6|1|Always 1|-|7|00|C0=0..R0-1 : VMA.Lsb=0xFFC0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)|} {| class="wikitable"! R11 - Bit number! Bit value! Event|-|0|0|C4=R4 and C9=R9 and C0=R0 : Last char of screen|-|1|0|C4=R6-1 and C9=R9 and C0=R0 : Last char displayed|-|2|0|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync|-|3|0/1|Timer 16 CRTC frames|-|4|1|Always 1|-|5|0|C9=R9 : C0=0 to R0|-|6|0|Always 0|-|7|1|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)|} <br>
=== Horizontal and Vertical Sync (R3) ===
Type 0:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed , this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed , no HSYNC is generated (and therefore, no interrupts).
Type 1:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed , no HSYNC is generated (and therefore, no interrupts).
Type 2:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed , this gives a HSYNC width of 16.
Types 3/4:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed , this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed , this gives a HSYNC width of 16.
<br>
*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 3..2 are ignored.
*Bits 1..0 define the interlace mode (00 = No Interlace; 01 = Interlace Sync; 10 = No Interlace; 11 = Interlace Sync and Video).
Types 1/2:
*Bits 7..2 are ignored.
*Bits 1..0 define the interlace mode.
 
[[File:CRTC Interlace modes.png]]
 
For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2.
 
==== Interlace sync mode (ISM) ====
 
In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary.
 
==== Interlace sync and video mode (IVM) ====
 
In this mode, alternating lines are displayed in the even and odd field to double the resolution.
 
On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd.
 
It is necessary to reprogram the CRTC as if we were building a frame of 624 lines.
 
CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line.
 
==== Interlace adjustment line ====
 
On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode.
<br>
<br>
==UM6845R and R12/R13 = Status register on Type = The UM6845R differs to other CRTC in respect of R12/R13.  When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.  Just like other CRTCs when RC==(R9-1 ), the current MA is captured for the next char-line. In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start. == UM6845R status register ==
The UM6845R has a status register that can be read using port &BExx.
All the other bits read as 0 and don't have any function.
<br>== CRTC Type Detection ==
== It is possible to detect the CRTC Type using software methods, and this is done to:  * warn that the software was not designed for the detected 6845 and may function incorrectly* to adapt the software so that it will run with the detected 6845 * In most cases, the type of the detected 6845 is reported Detection ==routine in BASIC:
<pre>
10 MODE 1:' Reinitialize screen
</pre>
Distinguishing between CRTCs 3 and 4 can be done by trying to [[Programming:Unlocking ASIC|unlock the ASIC]] or by testing the [[8255|PPI chip]]. On ASIC, if PPI Port B is set as output it will behave the same as input.
<br>
<br>
== Internal Counters Block Diagrams ==
{| class="wikitable"
! Counter name
! Abbr
! Alternate name
! Comment
|-
|Horizontal Character Counter!Hitachi|HCC!UMC|C0| Increments on every clock cycle!Motorola
|-
|Horizontal Sync Counter|HSC|C3l||-|Vertical Character Counter|VCC|C4||-|Vertical Sync Counter|VSC|C3h|-|Vertical Line Counter|VLC|C9|If not in IVM mode, this counter is exposed on [[File:CRTC pins RA0Block Diagram..RA4png|-Hitachi]]|Vertical Total Adjust Counter|VTAC|C5|This counter does not exist on CRTCs 0/3/4[[File:UMC CRTC Block Diagram. C9 is reused insteadpng|-UMC]]|Frame Counter|FC||Used to alternate frames in interlace and for [[File:Motorola CRTC cursor blinkingBlock Diagram.png|-|Memory Address|MA||This counter is exposed on CRTC pins MA0..MA13Motorola]]
|}
 
When IVM mode is activated, VLC continues to increment normally. However, RA is not identical to VLC anymore. Instead, VLC is considered shifted left by 1 bit, and bit0 represents the parity of the field (even/odd).
 
<br>
 
== CRTC counter differences ==
 
=== MA buffering ===
 
No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. The buffer MA' is needed because MA has to be reloaded at the beginning of every raster line.
 
At the end of the display of the last raster line of each character line (ie. when HCC=R1 and VLC=R9), MA' captures the current value of MA.
 
CRTC 2 is the exception: at the end of the display of the last raster line of the frame, MA' captures R12/R13 instead of MA.
 
<br>
 
=== MA reload ===
 
On CRTCs 0/3/4, at the beginning of the first raster line of the frame, MA and MA' are loaded with R12/R13. Otherwise, MA is loaded with MA'.
 
On CRTC 2, at the beginning of every raster line of the frame (including the first one), MA is loaded with MA'.
 
On CRTC 1, at the beginning of every raster line of the first character line of the frame (ie. when VCC=0), MA is loaded with R12/R13 instead of MA'. '''This is a major source of incompatibility if the programmer does not take care.''' In demos and games, to be compatible with all CRTCs, program R12/R13 only when VCC≠0. This will then take effect at the next CRTC frame start.
 
==== Rupture For Dummies (R5 bug) ====
 
CRTC 1 has a bug that occurs when R5 is updated with a non-zero value when HCC=R0 and VLC≠R9, but only when R5 was previously 0. This changes the MA update source to R12/R13 instead of MA'. The CRTC then loads R12/R13 into MA at the beginning of every scanline, regardless of the VCC value.
 
This R5 bug also messes with the frame parity management. However, it is possible to fix the parity of the frame by activating/deactivating the IVM interlace mode.
 
The vertical adjustment operates normally after the RFD is triggered. If vertical adjustment is not needed, R5 can be reset at any time after the RFD is activated.
 
This CRTC bug divides the CPC community, with some considering it fully understood, while others find it still perplexing as it feels like the bug itself is bugged.
 
This effect is used in the [https://www.cpc-power.com/index.php?page=detail&num=19308 DSC4 demo].
 
<br>
 
=== VSC (C3h) overflow ===
 
During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.
 
On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.
 
<br>
 
=== HSC (C3l) overflow ===
 
During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.
 
The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.
 
<br>
 
=== VCC (C4) overflow ===
 
On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:
* if this update was done when VCC < R4, then VCC overflows and will count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
* if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame
 
The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow.
 
<br>
 
=== HCC (C0) overflow ===
 
If Horizontal Total (R0) is changed with a value less than the current HCC, then:
* on CRTCs 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0
* on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line
 
<br>
 
=== VLC (C9) overflow ===
 
If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:
* on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9
* on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line
 
As an exception, on CRTCs 0/2, if VLC is modified during the last frame line, then the updated value will not be considered for the current frame.
 
<br>
 
=== VTAC (C5/C9) overflow ===
 
During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:
* on CRTCs 0/1/2, VTAC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end
 
As an exception, on CRTCs 0/2, if VTAC is modified during the last frame line, then the updated value will not be considered for the current frame.
 
<br>
 
=== Vertical Adjustment mode ===
 
On CRTCs 3/4, this mode does not increment VCC, so VCC remains equal to R4.
 
On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once.
 
On CRTCs 1/2, this mode increments VCC, causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9.
 
Also, only CRTCs 1/2 have a dedicated C5 counter. On CRTCs 0/3/4, during Vertical Adjustment, C9 has to fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore.
 
<br>
 
=== Counter freezes ===
 
On CRTCs 1/2/3/4, R0 accepts all values without causing any problems for counters.
 
On CRTC 0:
* Setting R0 to 0 will cause numerous issues that stem from the fact that VLC is frozen. As HCC never reaches 1, the logic that increments VLC is never triggered.
* The logic that triggers vertical adjustment is broken if R0<2.
 
<br>
 
== Block Diagrams ==
 
=== Hitachi ===
 
[[File:CRTC Block Diagram.png]]
 
<br>
 
=== UMC ===
[[File:UMC CRTC Block Diagram.png]]
 
<br>
 
=== Motorola ===
[[File:Motorola CRTC Block Diagram.png]]
<br>
This chip was never used by Amstrad. However, some CPC enthusiasts have replaced the original CRTC chip in their CPC with this one.
With this chip, split-screen becomes easy: [https://thecheshirec.at/2024/05/20/des-splitscreens-en-basic-sur-crtc5/ Split-screen in BASIC]. And 3 new graphics modes (160x100x16160x100x16c, 320x100x4320x100x4c, 640x100x2640x100x2c) are available: [https://thecheshirec.at/2024/11/10/trois-nouveaux-modes-video-grace-au-crtc-5/ New graphics modes in BASIC].
This is the cheapest way to upgrade the CPC's graphics capabilities, costing only 1.29€. [https://thecheshirec.at/2024/05/19/des-crtc5-a-129e/ Source]
== Datasheets ==
 
==== Used by Amstrad ====
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [[Media:UM6845-UMC.pdf|UM6845 (UMC)]] aka Type 0
* [[Media:Um6845r.umc.pdf|UM6845R (UMC)]] aka Type 1
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola)]] aka Type 2 [[Media:Mc6845.pdf|Other datasheet version]]
* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3 ([[ASIC]])
* [[AMS40226 (Amstrad)]] aka Type 4 (Pre-ASIC)
 
<br>
==== Unused clones ====
* [[CM607P]] a Bulgarian clone made in Pravetz factory (maybe . It is used on [[KC Compact]] and in the [[Aleste 520EX]])* [[Media:EF6845P.pdf|EF6845]] by Thomson Semiconductors* [[Media:hd6845.hitachi.pdf|HD6845R]] by Hitachi. According to Kevin Thacker, the [[KC Compact]] used HD6845R only.
* [[Media:UM6845E-UMC.pdf|UM6845E]] by UMC
* [[Media:Mc6845.pdf|MC6845-1]] by Motorola
* [[Media:F6845.pdf|F6845]] by Fairchild
* [[Media:EF6845P.pdf|EF6845]] by Thomson Semiconductors* [[Media:VL6845 VTi.pdf|VL6845]] by VTi* [[Media:C6845 CRTC (CAST).pdf|C6845]] by Cast* [[Media:MB89321B FUJ.pdf|MB89321B]] by Fujitsu. It is pin-compatible with the 6845* [[Media:MB89321A datasheet CRTC.pdf|MB89321A]] by Fujitsu. Enhanced version that adds smooth scroll, screen partitioning, independent scrolling of screen partitions, and other convenient features* [[Media:Mos 6545-1 crtc.pdf|CRTC MOS 6545]] (MOS, Rockwell, Synertek) is pin-compatible with the 6845 and only has minor . Its differencesare found in the R8 register.* [https://www.cpcwiki.eu/forum/other-retro/interesting-discussion-about-the-c128-s-cpm-poor-performance/msg223058/#msg223058 MOS 8563] It is an evolution of the 6545/6845 CRTC chip, with blitter abilities to autonomously perform block memory copies within its dedicated video RAM.
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845
* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [[Media:ACCC1.8-EN.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
* [[Media:CRTC Compendium Podcast.mp3]] The CRTC Compendium digested in podcast format
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [https://pulkomandy.github.io/shinra.github.io/crtc.html PulkoMandy's table] [https://www.theoddys.com/acorn/the_6845_crtc/6845%20Variants.xlsx Oddy's table] Differences between CRTC types]
* [[Media:Dossier Rupture(Gozeur Paradox).pdf]]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [[Mediahttps:ACCC1//martin.8-ENhinner.pdf]] [[Media:ACCC1.8-FR.pdf]] CPC CRTC Compendium - Latest (04info/2024!) document containing in-depth info about CRTC programming on CPCvga/pal.* [[Media:CRTC Compendium Podcast.mp3]html PAL video timing specification] The CRTC Compendium digested in podcast format <br>
==Related pages==
*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.
 
*[[VIDI digitizer]] This extension contains its own CRTC chip
[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]
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